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1. Quartus II 编程环境的使用练习，验证4线-2线优先编码器。
2. 用Verilog HDL语言设计一个8线-3线优先编码器。
表7.4 8线-3线优先编码器的功能表 | |||||||||||||
输入 | 输出 | ||||||||||||
S | I0 | I1 | I2 | I3 | I4 | I5 | I6 | I7 | Y2 | Y1 | Y0 | YS | YEX |
1 | × | × | × | × | × | × | × | × | 1 | 1 | 1 | 1 | 1 |
0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
0 | × | × | × | × | × | × | × | 0 | 0 | 0 | 0 | 1 | 0 |
0 | × | × | × | × | × | × | 0 | 1 | 0 | 0 | 1 | 1 | 0 |
0 | × | × | × | × | × | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 |
0 | × | × | × | × | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
0 | × | × | × | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 |
0 | × | × | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
0 | × | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
3. 用Verilog HDL语言设计一个二-十进制译码器。
表7.5 二十进制译码器的功能表 | ||||||||||||||
序列 | 输入 | 输出 | ||||||||||||
A3 | A2 | A1 | A0 | Y0 | Y1 | Y2 | Y3 | Y4 | Y5 | Y6 | Y7 | Y8 | Y9 | |
0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
2 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
3 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 |
4 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 |
5 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 |
6 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 |
7 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 |
8 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
9 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
10-15 | 1010-1111为伪码 | 输出端全部无效，既全为逻辑1 | ||||||||||||
4. 用Verilog HDL语言设计一个满足下表要求的组合逻辑电路。
| 输入 | 输出 | ||||||
| IN2 | IN1 | R1 | Y1 | G1 | R2 | Y2 | G2 |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
| 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 |
| 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 |
| 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 |